In semiconductor fabrication integrated circuits and semiconductor devices are formed by sequentially forming semiconductor device features (structures) in sequential layers of material in a bottom-up manufacturing method. In order to form reliable devices, close tolerances are required in forming features, for example metal lines, to achieve precise control of the electrical resistance. Such electrical resistance is frequently measured as a sheet resistance (Rs) of the metal lines.
Often prior art processes rely on CMP (Chemical Mechanical Planarization) methods to control final metal line thickness, which in turn directly affects sheet resistance uniformity. For example, in a damascene metallization process, one or more dielectric insulating layers are formed, followed by anisotropic etching to define a trench opening in the dielectric insulating layer. Following formation of the trench, metal is deposited to fill the trench opening and form the metal line. A CMP process is then performed to planarize the upper surface of the process wafer and to define the final dimension of the line.
In forming metal lines, which also are often referred to as conductive interconnections, copper is increasingly used. Copper has low resistivity and good electromigration resistance as compared to other traditional interconnect metals such as aluminum. As device sizes decrease ever further, it is becoming more important to precisely control the width and depth of the metal lines in order to precisely control the resistance of the metal lines.
As previously noted, in many current processes the final thickness of the metal lines was controlled by controlling CMP polishing times that were determined from expected results based on previous model processes. If process deviations unexpectedly contribute to a less than desirable metal line thickness (i.e., sheet resistance), there is little that can be done to correct the problem especially if the CMP process has removed an excessive amount of the metal line.
Prior art attempts at controlling deviations have employed CMP devices having “multi-zone” heads, which are designed to remove material at different rates across a single wafer. Still, these CMP techniques have not been effective for use with copper line structures, in part because copper-CMP involves substantial chemical removal of material as compared to the more traditional mechanical removal of material experienced with other metal materials. Thus, sheet resistance can vary widely within a single wafer, as illustrated in FIG. 1, in which the X and Y axes represent wafer test sites, and the Z axis represents Copper sheet resistance. As can be seen, the sheet resistance of the copper trenches measured at different locations on a single wafer may be widely varying.
Thus, there remains a need in the semiconductor art for an improved system and method for achieving improved metal line electrical resistance precision, and for providing greater control over the final sheet resistance of copper-filled trenches.